集成电路设计的开源EDA软件Yosys(3)

# read design
read_verilog counter.v
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
# low-level synthesis
techmap; opt
# map to target architecture
dfflibmap -liberty cmos_cells.lib
abc -liberty cmos_cells.lib
# split larger signals
splitnets -ports; opt
Download:show_cmos.ys
library(demo) {
cell(NOT) {
area: 3;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: A; }
}
cell(BUF) {
area: 6;
pin(A) { direction: input; }
pin(Y) { direction: output;
function: A; }
}
cell(NAND) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: (A*B); }
}
cell(NOR) {
area: 4;
pin(A) { direction: input; }
pin(B) { direction: input; }
pin(Y) { direction: output;
function: (A B); }
}
cell(DFF) {
area: 18;
ff(IQ, IQN) { clocked_on: C;
next_state: D; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: IQ; }
}
}
Download:cmos_cells.lib
粗粒度网表

# read design
read_verilog counter.v
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
# mapping coarse-grain cells
extract -map coarse_cells.v
Download:show_coarse.ys